Open Source Hardware Development Board Available

While it’s not going to displace even a Raspberry Pi Model B+ in terms of performance, it’s a start. Things will only get better and faster from here.

At long last, after years and years of waiting, there’s an open source CPU chip already built onto a development board that you can buy and use. The $59 price is very affordable. This matters as the various main line CPU vendors have been pressured into putting ever more weaknesses ( i.e. what looks like potential back doors) into their hardware for various government TLAs (Three Letter Agencies).

So what’s the base project / CPU design group?


RISC-V (pronounced “risk-five”) is an open instruction set architecture (ISA) based on established reduced instruction set computing (RISC) principles.

In contrast to most ISAs, the RISC-V ISA can be freely used for any purpose, permitting anyone to design, manufacture and sell RISC-V chips and software. While not the first open ISA, it is significant because it is designed to be useful in modern computerized devices such as warehouse-scale cloud computers, high-end mobile phones and the smallest embedded systems. Such uses demand that the designers consider both performance and power efficiency. The instruction set also has a substantial body of supporting software, which fixes a usual weakness of new instruction sets.

The project began in 2010 at the University of California, Berkeley, but many contributors are volunteers and industry workers outside the university.

The RISC-V ISA has been designed with small, fast, and low-power real-world implementations in mind, but without over-architecting for a particular microarchitecture style.
The RISC-V authors aim to provide several CPU designs freely available under a BSD license. Such licenses allow derivative works, such as RISC-V chip designs, to be either open and free, like RISC-V itself, or closed and proprietary.
Commercially available

SiFive has developed an embedded system on chip, compatible with Arduino, for sale at $59 that began selling in May 2017.

Codasip and UltraSoC have developed fully supported intellectual property for RISC-V embedded SOCs that combine Codasip’s RISC-V cores and other IP with UltraSoC’s debug, optimization and analytics.
Imperas has developed a family of fast processor models for the different subsets of RV32G and RV64G ISA variants that are part of the OVPsim instruction accurate simulator distributions used for embedded software development.

In development

The Indian Institute of Technology Madras is developing six RISC-V open-source CPU designs for six distinct uses, from a small 32-bit CPU for the internet of things (IoT) to large, 64-bit CPUs designed for warehouse-scale computers such as server farms based on RapidIO and Hybrid Memory Cube technologies.
Nvidia plans to use RISC-V to replace their Falcon processor on their GeForce graphics cards.
ASTC in Adelaide developed a RISC-V CPU for embedded ICs.
A founder of Adapteva plans to use RISC-V, in a successor to their manycore accelerator product
lowRISC is a non profit project that aims to implement a fully open-source system on a chip (SoC) based on the 64-bit RISC-V ISA.
The Computer Laboratory, University of Cambridge, in collaboration with the FreeBSD Project, has ported the FreeBSD operating system to 64-bit RISC-V to use as a hardware-software research platform.
ETH Zurich and the University of Bologna have cooperatively developed the PULPino processor as part of the PULP (Parallel Ultra-Low Power) project using RISC-V

So the “in development” is interesting in terms of a list of dreams. Server farms made of 64 bit CPUs, all provably non-buggered from the design stage. But what about NOW?

Well, that’s the first line. SiFive has a devo board you can buy today. The specs make it usable in small embedded systems and robotics, but a bit too light for even a command line only desktop. For now…

SiFive is a fabless semiconductor company that produces computer chips based on the RISC-V instruction set architecture (ISA) SiFive’s products include SoC’s and development boards.

SiFive is the first company to produce a chip that implements that RISC-V ISA.


SiFive was founded in 2015 by Krste Asanovic, Yunsup Lee, and Andrew Waterman, three researchers from the University of California Berkeley. On November 29, 2016, SiFive released the Freedom Everywhere 310 SoC and the HiFive development board, making SiFive the first company to produce a chip that implements that RISC-V ISA, although universities have produced earlier RISC-V processors.

In August 2017, SiFive hired Naveed Sherwani as CEO. In October, SiFive did a limited release of its U54-MC, reportedly the world’s first RISC-V based 64-bit quad-core CPU to support fully featured operating systems like Linux.
SiFive’s business model is based on designing custom computer chips for other businesses. SiFive also produces the FE310 microcontroller and the HiFive1 development board.

OK, so quad core 64 bit sounds good. What’s that full up board?

A RISC-V-based, Open-Source, Arduino-Compatible Development Kit

The HiFive1 is an Arduino-Compatible development kit featuring the Freedom E310, the industry’s first commercially available RISC-V SoC.
HiFive1 Features & Specifications

Microcontroller: SiFive Freedom E310 (FE310)
SiFive E31 RISC-V Core
Architecture: 32-bit RV32IMAC
Speed: 320+ MHz

Performance: 1.61 DMIPs/MHz, 2.73 Coremark/MHz
Memory: 16 KB Instruction Cache, 16 KB Data Scratchpad
Other Features: Hardware Multiply/Divide, Debug Module, Flexible Clock Generation with on-chip oscillators and PLLs
Operating Voltage: 3.3 V and 1.8 V
Input Voltage: 5 V USB or 7-12 VDC Jack
IO Voltages: Both 3.3 V or 5 V supported
Digital I/O Pins: 19
PWM Pins: 9
SPI Controllers/HW CS Pins: 1/3
External Interrupt Pins: 19
External Wakeup Pins: 1
Flash Memory: 128 Mbit Off-Chip (ISSI SPI Flash)
Host Interface (microUSB): Program, Debug, and Serial Communication
Dimensions: 68 mm x 51 mm
Weight: 22 g

OK, so they have two chips with similar “Freedom” names, but one is 32 bit on the board and the other is a quad core 64 bit… The board runs at 320 MHz, so not a barn burner. Figure it’s about 1/2 of a Pi B+ as a first guess. (Comparing actual benchmarks would be better, so a Dig Here! is to look up DMIPs and Coremark numbers for the Pi.)

Interface is via microUSB, so not going to plug in your HDMI monitor and go… Clearly the market for this is things like small routers, home WiFi hotspots, and DIY cellphones. Oh, and things like robotics and process / device controllers. Not desktops…

Lists there SOC products. The fastest one looks very interesting to me:

Freedom Unleashed

The Freedom Unleashed family features a series of customizable Unix-capable SoC platforms, based on SiFive’s U5 Core IP Series, the world’s most advanced multicore RISC-V CPUs. The first member of the Freedom Unleashed family, the U500 platform targets initial customers in diverse markets such as machine learning, storage, and networking.

Freedom U500 Platform

U5 Core IP Series at 1.6GHz+
RV64GC Architecture
Multicore, Cache Coherency Support
High Speed Peripherals: PCIe 3.0, USB3.0, GbE, DDR3/4
TSMC 28nm

Multicore at 1.6 GHz we’re getting somewhere very interesting. GbE and USB 3.0 are nice too.

Unfortunately, the dev kit for it is a FPGA (Field Programmable Gate Array) and not a real CPU chip, so speed is not going to be the same, nor costs:

Freedom U500 VC707 FPGA Dev Kit

The Freedom U500 VC707 FPGA Dev Kit is the most powerful way to prototype and develop for RISC-V. Featuring SiFive’s U5 Core IP Series, the world’s most advanced RISC-V CPU, this kit is the ideal way to start developing advanced OS capabilities and software applications. This development kit also features high speed serial interfaces allowing for system prototyping with PCIe, USB, or GbE interfaces.

The VC707 FPGA Dev Kit consists of the Xilinx Virtex-7 FPGA VC707 Evaluation Kit plus many optional components.

Clicking their “BUY” link takes you to Avnet where you can buy one for a “mere” $3500…

Your Price: USD $3,495.00
Lead time: 2 weeks

The Virtex®-7 FPGA VC707 Evaluation Kit is a full-featured, highly-flexible, high-speed serial base platform using the Virtex-7 XC7VX485T-2FFG1761C and includes basic components of hardware, design tools, IP, and pre-verified reference designs for system designs that demand high-performance, serial connectivity and advanced memory interfacing. The included pre-verified reference designs and industry-standard FPGA Mezzanine Connectors (FMC) allow scaling and customization with daughter cards.

What’s Included

VC707 evaluation board featuring the Virtex-7 XC7VX485T-2FFG1761C FPGA
Full seat Vivado® Design Suite: Design Edition
Node locked & Device-locked to the Virtex-7 XC7VX485T FPGA, with 1 year of updates and support
Getting Started Guide (Web)
Board Design Files (DxDesigner 2005, Allegro 16.3 – 16.5)
AMS 101 evaluation board
Cables & Power Supply
90-day limited warranty

Key Features

40Gb/s Connectivity platform for high-bandwidth and high-performance applications using Virtex-7 VX485T FPGAs
Hardware, design tools, IP, and pre-verified reference designs
Advanced memory interface with 1GB DDR3 SODIM Memory up to 800MHz / 1600Mbps
Enabling serial connectivity with PCIe Gen2x8, SFP+ and SMA Pairs, UART, IIC
Supports embedded processing with MicroBlaze, soft 32bit RISC
Develop networking applications with 10-100-1000 Mbps Ethernet (GMII, RGMII and SGMII)
Expand I/O with the FPGA Mezzanine Card (FMC) interface

Well, at that price I guess I’m going to wait for that motivation to set up a Kickstarter Campaign to kick in ;-)

At least it’s a start. Somewhere someone will be getting one of these and launching a Kickstarter to make a Pi Like Board but without the licenses and opaque binary blobs. It will sell. (I’ll buy one up to $100, maybe more…)

I’d guess the ‘lead time’ is about 2 years from now to first product. Faster if well funded.

At that point, you have Free and Open Source from hardware to desktop. Major remaining risks would just be who does the actual fab and do they stick in something unexpected / clandestine. As these are boards going to low level developers, I’d expect “oddities” to stand out “right quick”. Someone, somewhere, will dump and disassemble any firmware. Someone in QA somewhere will SEM (Scanning Electron Microscope) some die and see what’s really been fabbed. Even if it’s just a grad student doing it as a project for extra credit.

So I’m marking my calendar. Sometime around 2019 I’ll be expecting to put one of these, as a SOC (System On Chip) based SBC (Single Board Computer), on my desktop, and boot Devuan.

I have a friend who teaches robotics. I might buy him the $59 board as a Christmas present… then get him to teach me how to use it in robots ;-)

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About E.M.Smith

A technical managerial sort interested in things from Stonehenge to computer science. My present "hot buttons' are the mythology of Climate Change and ancient metrology; but things change...
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15 Responses to Open Source Hardware Development Board Available

  1. E.M.Smith says:

    Looks like back in April the Arch Linux folks started porting to the $59 low end board.

    so there will be a Linux on it and it’s got enough “juice” for many SSH console only headless things. As soon as I can find a working Linux port for it, I’m likely going to buy one. Just to support the “cause” of open source computing from hardware to keyboard…

  2. E.M.Smith says:

    Kernel port:

    Debian is going for the 64 bit chip:

    Fedora is doing the 64 bit too:

    RISC-V (pronounced “RISC Five”) is an open source instruction set architecture (ISA). This project, informally called Fedora/RISC-V, aims to provide a complete Fedora experience on the RISC-V (64 bit, RV64G) architecture.

    Status April 2017 The port is usable as-is. But we are waiting for glibc and the kernel support to go upstream. At that point we will re-bootstrap the whole project using the final ABIs. This is expected to happen in the next few months.

    Status November 2016 The port supports about two thirds of the packages in Fedora 25, so it is quite complete and ready to use. Most important command-line programs just work (and even a few graphical ones). However if you are using your own hardware then you will need to supply a compatible kernel and bootloader and just use the Fedora userspace. Fedora/RISC-V does not support 32 bit or embedded hardware.

    So for most Risc-V stuff you need the unready 64 bit board (or a lot of cash for the FPGA) and there might be a bootstrap onto the 32 bit available with some DIY on the rest of the system… Or maybe better than that with more digging.

    What’s pretty clear to me is that some Big Names are on board with the RISC-V architecture coming out the gate. I think this puppy is gonna take off. Also found references to Samsung using it for controllers in some of their gear (i.e. no ARM license fees).

    At this point I’m pretty sure I’m going to get one even if just to play with it.

  3. jim2 says:

    CIO – Do you know of any security (as in backdoors) problems with peripheral chips? UARTS, network chips, anything else?

  4. E.M.Smith says:

    Most problems with peripherals are from folks writing kits into the flash on things like disk controllers or USB sticks. Not heard of any exploits using UARTS or network chips, but to be certain one would need to do a CERT search.

    Part of why I like using SD cards in a carrier instead of a USB stick is that the SD cards are typically used in cameras and other “uninteresting” things and many are used by low level programmers who tend to snoop into them so likely to catch if they are buggered. USB sticks mostly used with computers directly, and not often closely inspected (and I know personally of at least one batch shipped from China pre-buggered with a virus / entry point in 10% of the shipment…)

    Also, most of the kit used is PC specific, so just being on a different platform blocks most of it, if it is there at all.

    I tend to fully format any new USB Stick or hard drive upon first installation (and that first installation is onto a Linux box that’s subject to reflash of the OS image…). While that doesn’t erase all potential kits, it erases most of the simple ones.

  5. Larry Ledwick says:

    Current laptops almost always have an SD memory chip slot, so that assumption is probably not accurate anymore.

    That means lots of SD chips get inserted in laptops to down load camera photos etc.

  6. E.M.Smith says:


    Why I used micro-SD cards in adapters ;-)

    But yes, all assumptions have limitations and timers… But “so far so good”! (as he passes the 12th floor of a 50 story building… ;-)

    At one time, just to see if I could do it, I installed an emulator onto an SD card in a corporate PC that was “locked down” and then proceeded to run Solaris in the emulator. It was slow, but worked. So there I was, on the corporate network, with root on a Unix box ;-)

    As I was working in the security department, I figured it was likely to be “OK” if I had to ‘splain myself… but when my boss found out about it (whom I’ve worked with on and off at a half dozen different companies over the decades since about 1982…) he asked me politely if I could not do that anymore as he didn’t want to explain it to others ;-)

    It was fun, though. Having a completely I.T. department controlled PC with the finest security Microsoft could provide, and just bypassing it all with an SD card with an .exe on it…

    On the same machine, I moved my MS email (Lookout? Outlook? Something like that ;-) directories onto an SD card too. So all my email never hit the hard disk. Mostly I was just playing with the feature to see what all I could do. ( I’d get bored some times waiting for tests and such to finish ;-)

    What was interesting was that a lot of the “usual suspects” of forensics detritus that MS Windows leaves all over the place could be redirected at the SD card. I never did all of it at the same time, but it ought to work too. When it was time to leave, “scrubbing” my computer was very easy. Format the chip ;-)

    I could also just pop the SD card when leaving the desk for a while and know that my security oriented files were not available to anyone sitting down at the computer. So it can be used as a “logoff offline data” feature. (All contractors were in one part of one floor in shared space, so lots of other company folks in and out during a month.)

    I still get a chuckle out of remembering how strange the PC Monitor looked with a Solaris login screen ;-) It was also fun when my boss walked up and saw a Solaris Desktop open… that whole “He’s at it again…” thing ;-) You know; when folks can see you’ve done some kind of FM, and they hired you because you can do FM, but they don’t want you to do that FM, but they know that they can trust you (since basically they don’t have a choice and with decades of ‘knowing’ each other the know the person’s values and principles), but still it leaves them thinking about a world of some who can cast Magic spells and corporate types who “don’t get it”… and them in between the two as buffering agent…

    As we had Lenovo laptops in cradles with real monitors, I was a bit worried about the potential for Chinese “crap” hidden in them (post sale by IBM to Lenovo of the ThinkPad, the corporate standard was not reevaluated…) I found I was more comfortable knowing that “my stuff” was only “online” when I was logged on and looking at the screen and / or system activity status.

    A 64 GB chip holds a whole lot of email and files… I never came close to filling it up.

  7. dai davies says:

    Thanks for the post, EM. Boosted my confidence in the possibility of a private future to replace the hazy image disappearing in the rear view mirror.


  8. p.g.sharrow says:

    that SD OS RasPi is kind of cool for that. just a fingernail size chip contains everything…pg

  9. E.M.Smith says:


    You are most welcome!

    Nice to know someone else cared about it. It was a bit on the technical geek edge and I wasn’t sure how many folks would really find it interesting.

    I’m currently planning on buying a 64 bit quad core version whenever it hits a SBC form factor product. Preferably one with Debian on it that can be ‘uplifted’ to Devuan and running open source boot loader. At that point, I’m pretty sure I’ve got security.

    I looked at the ISA. Turns out it is a kit of ISA’s. You can choose parts to put in your chip, or not. Things like the ARM Thumb smaller instructions for more compact code for the most common instructions, float hardware, etc. etc. I hate it when chip makers do that as it means not ONE chip, but 20 variations, and the compiler has to be able to figure out what each one has in hardware and when to supply software workarounds. UNfortunately, this usually means the first releases of Linux and the Tool Chain are written for the minimal subset and you end up buying a chip with all that cool hardware and then not using it for the next 4 years as things slowly get added to the tool-chain smarts and the OS starts to use them. (Like using NEON for HW vector floats in the ARM – it can be done, but most generic Linux kernels and releases don’t do it).

    Oh Well, it leads to much wider chip adoption as vendors making very low power things that don’t need float can just not fab that part into the chip, and those that do a lot of math can put it in… and eventually the tool chain (compilers, assemblers, etc.) and the OS learns to detect and use them if present. I’m just glad I’m not in charge of doing Compiler Maintenance on the tool chain ;-) (I used to do Q.A. on such a compiler tool chain for something like 72 different hardware sets – it was a challenge to write code that ran on all of them with one set of sources…)

    But yes: This is going to be easily validated hardware with hard to factory bugger architecture. (i.e. no “management engine” like crap in it without violating the ISA) Then layer on some Open Source software and you’ve got yourself 99%+ comfort and confidence ;-) Add an IDS / IPS and some DNS local and a VPN to another country and pour a tall one 8-)

  10. E.M.Smith says:

    Description of the ISA (Instruction Set Arch.) here:

    Some of the “mix and match” choices available:

    RISC-V segregates math into a minimal set of integer instructions (set “I”) with add, subtract, shift, bit-wise logic and comparing-branches. These can simulate most of the other RISC-V instruction sets with software. (The atomic instructions are a notable exception.) RISC-V currently lacks the “count leading zero” and bit-field operations normally used to speed software floating-point in a pure-integer processor.

    The integer multiplication instructions (set “M”) includes signed and unsigned multiply and divide. Double-precision integer multiplies and divides are included, as multiplies and divides that produce the “high word” of the result. The ISA document recommends that implementors of CPUs and compilers “fuse” a standardized sequence of high and low multiply and divide instructions to a single operation if possible. RISC-V’s ISA document also recommends fusing a multiply-accumulate operation. (Multiply-accumulate is a core primitive of both digital signal processing and numerical linear algebra, and so is incorporated as part of a common benchmark, Coremark.

    The floating-point instructions (set “F”) includes single-precision arithmetic and also comparison-branches similar to the integer arithmetic. It requires an additional 32 floating-point registers. These are separate from the integer registers. The double-precision floating point instructions (set “D”) generally assume that the floating-point registers are 64-bit (i.e. double-width), and the “F” subset is coordinated with the “D” set. A quad-precision 128-bit floating-point ISA (“Q”) is also defined. RISC-V computers without floating-point can use a floating-point software library.
    The compressed set

    The standard RISC-V ISA specifies that all instructions are 32 bits. This makes for a particularly simple implementation, but like other RISC processors with such an instruction encoding, results in larger code size than in other instruction sets. To compensate, RISC-V’s “32-bit” instructions are actually 30 bits;  3⁄4 of the opcode space is reserved for an optional (but recommended) variable-length “compressed” instruction set, RVC, that includes 16-bit instructions. Like ARM’s Thumb and the MIPS16, the compressed instructions are simply aliases for a subset of the larger instructions. Unlike ARM’s Thumb or the MIPS compressed set, space was reserved from the beginning so there is no separate operating mode. Standard and compressed instructions may be intermixed freely. (letter “C”)

    Because (like Thumb-1 and MIPS16) the compressed instructions are simply alternate encodings (aliases) for a selected subset of larger instructions, the compression can be implemented in the assembler, and it is not essential for the compiler to even know about it.

    A prototype of RVC was tested. The prototype code was 20% smaller than an x86 PC and MIPS compressed code, and 2% larger than ARM Thumb-2 code. It also substantially reduced both the needed cache memory and the estimated power usage of the memory system.

    The researcher intended to reduce the code’s binary size for small computers, especially embedded computer systems. The prototype included 33 of the most frequently used instructions, recoded as compact 16-bit formats using operation codes previously reserved for the compressed set. The compression was done in the assembler, with no changes to the compiler. Compressed instructions omitted fields that are often zero, used small immediate values or accessed subsets (16 or 8) of the registers. addi is very common and often compressible.

    Much of the difference in size compared to Arm’s Thumb set occurred because RISC-V, and the prototype, have no instructions to save and restore multiple registers. Instead, the compiler generated conventional instructions that access the stack. The prototype RVC assembler then often converted these to compressed forms that were half the size. However, this still took more code space than the ARM instructions that save and restore multiple registers. The researcher proposed to modify the compiler to call library routines to save and restore registers. These routines would tend to remain in a code cache and therefore run fast, though probably not as fast as a save-multiple instruction.

    The embedded subset

    An instruction set for the smallest “embedded” CPUs (set “E”) is reduced in other ways: Only 16 of the 32-bit integer registers are supported. Floating-point instructions should not be supported (the specification forbids it as uneconomical), so a floating-point software library must be used. The compressed set “C” is recommended. The privileged instruction set supports only machine mode, user mode and memory schemes that use base-and-bound address relocation.

    Correspondents have proposed even smaller, nonstandard, 16-bit “RV16E” ISAs: One would use a 16×16-bit integer register file, using the standard “EIMC” ISAs (including 32-bit instructions.) Another proposal would only use the 16-bit “C” instructions with an 8×16-bit register file. A full RV16EG was said to be possible with a completely recoded ISA.

    There is also a proposed vector instruction set and a SIMD option proposed. So the choices of ISA to actually fab will increase over time.

    Oh Well, not my problem. It’s the assembler and compiler and kernel guys who have to deal with it.

    For me the only impact of all this is that one will need to pay attention to exactly which bits of hardware are actually built in any particular RISC-V chip being sold. So, like the ARM family, you will have a set of letters after RV32 or RV64 listing just which hardware implementation of particular instructions are included on your particular chip. Oh Well. (Were it me, I’d have float hardware included in all chips. Then again, I don’t design I(di)OT devices nor microwave oven controllers…)

  11. dai davies says:


    Not afraid of a bit of geek stuff, but I’m way out of date. Had to go to Wiki to make sure I knew what an SD card was. Cut my teeth in the early 60s refurbishing an ex navy communications receiver so I could spend my evenings surfing the ionosphere – the internet of my youth. The last thing I built was a card for the Apple II.

    Now I write future fiction inspired by decades of thinking about how we can adapt to living in a high surveillance world and still maintain a tad of privacy/freedom. Not a new problem, of course. Hard to keep a secret in a country village.


  12. E.M.Smith says:


    Likely my growing up in a “country village” of a couple of thousand where you could not change your socks without tongues wagging, and enjoying the sheer joy of mild anonymity in The Big City; is the reason I advocate for electronic privacy.

    Per the RISC-V:

    The instruction set stuff basically says the ultimate chip design has things like Float hardware, video cores, compressed instruction sets and a few other things that if all are fabbed up on a chip, would make a fairly high end costly chip. Folks making stupid gizmos with trivial programming (like electronic photo displaying picture frames or microwave ovens) they care about 1 ¢ / core cost lift… so the definition of the ISA Instruction Set Architecture lets you choose what blocks to include in your chip for cost reasons.

    Compiler and assembler writers would like to just know that a given chip type includes Float of 32 bit (or whatever) and be done. Having “mix and match” instruction set blocks means they have a matrix of N x M and must adjust their code generation accordingly. A pain, but since ARM and Intel already have them doing it, might as well design your new ISA to do the same thing, I guess.

    I’m hopeful the multicore 64 bit with float and all, will be available on a SBC like the Pi inside a couple of years for under $100. Then I’ll finally have my secure Open Source hardware.

  13. dai davies says:

    Your plug-in computer story reminded me of the CPM card (Z80?) for the Apple II that I still have somewhere but with nothing to plug it in to. It was made, or at least badged, by Microsoft.


  14. E.M.Smith says:

    Well, I still have an Apple IIc “new in box” in my garage. Maybe our garages ought to share ;-)

    When I worked at Apple, one of the perks was that once a year you could by the latest product at a deep discount. Well, one year I bought an Apple IIc for my then too young child. By the time they got interested enough, I’d bought something more interesting and this box didn’t get used. So there it sits…

    I think I’ve got somewhere around a half dozen to a dozen computers in the garage; from Z80 based to a few Apple II to Macs to an old Apple TV (that is useless now that they have changed the broadcast standard to HDTV…) to… Maybe I ought to contact a museum …

    But yeah, it’s been an interesting journey from a computer as a suitcase sized box to complete Unix OS on a mini-SD card the size of my little finger fingernail…

    One of my muses (not yet implemented) is a Pi like mini-board (like a Nano something) serving up files as a file server, then you mount that onto some random PC (so it would need WiFi or ethernet access ) and then launch a guest OS from it. Now you don’t even have an SD card stuck into the PC… The SD card approach doesn’t require network access so is easier to do, but the network based option (while requiring some kind of network credentials) does not require particular hardware or physical evidence poking out of your computer when someone walks up. Eventually I’d like to try a “cloud based” OS image, but that’s a long ways off.

    UPDATE: FWIW, this interest in other ways of loading an OS began when I had a contract in San Francisco to remove all the floppy disk drives from their standard White Box PCs. They had a bunch of phone stations where the folks just needed a keyboard and monitor and CPU, no I/O external other than network, and their VP thought it a good idea to simply remove any IO facilities for possible non-approved software so as to encourage folks to only use the one approved application. Well, happy to take money to unplug devices, but makes doing software updates harder (then SW arrived on floppies, really those 3 something inch hard floppies). But it got me thinking about how to load software in “other ways”. Now that incudes loading a secure reliable personal OS image ;-)

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